A 9.8b-ENOB 5.5fJ/step fully-passive compressive sensing SAR ADC for WSN applications

Abstract

The emerging compressive sensing (CS) theory states that the sparsity of a signal can be exploited to reduce the ADC conversion rate. However, most previous CS frameworks still require dedicated analog CS encoders in front-of low-rate ADCs. Differently, this work proposes a fully-passive CS framework that directly embeds CS into a conventional SAR ADC, reducing the ADC power by 4 times. A prototype chip is fabricated in a 0.13µm CMOS process. Discrete-tone signals are converted and reconstructed with a peak SNDR of 61dB and a maximum signal sparsity of 8.2%. A 1-second long speech signal is also used to demonstrate the capability of the chip to compressively sense real-world signals. At 0.8V and 1MS/s, the CS-SAR ADC consumes 19.2µW in the Nyquist mode and 5µW in the CS mode. The peak FoM in the CS mode is 5.5fJ/step.