A 94.3-dB SFDR, 91.5-dB DR, and 200-kS/s CT Incremental Delta–Sigma Modulator With Differentially Reset FIR Feedback

Abstract

This letter presents a high-resolution continuous-time incremental delta-sigma modulator, which employs an finite impulse response (FIR) filter in its feedback. Due to the resetting environment of the incremental operation, the FIR digital-to-analog converter comes with added challenges to design. Thus, a differential resetting scheme between adjacent FIR taps is introduced, which allows the use of a sufficiently large number of taps in the incremental operation, leading to an improved clock jitter robustness, relaxed linearity, and dynamic requirements of the first stage opamp. A prototype is fabricated in a 180-nm CMOS process, occupying an active area of 0.175 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The prototype achieves a peak SNR/SNDR of 86/83 dB, a dynamic range (DR) of 91.5 dB, and a peak spurious-free DR of 94.3 dB at a conversion rate of 200 kS/s. The power consumption is 1.27 mW from a 3-V power supply. This results in a Schreier FoM of 170.4 dB.