Abstract
This paper proposes a low power spread spectrum clock generator (SSCG). The proposed SSCG is based on direct frequency synthesis and harmonic injection locking due to the highly digital frequency modulation and low power implementation. The prototype of the SSCG is implemented in 0.13 µm CMOS process. The proposed SSCG can generate 900 MHz spread spectrum signal with spread ratio of 1 %. The simulation results show that it has 35 dB EMI reduction and consumes 2.2 mW from 1.2 V supply.
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