A 900 MHz 1.2 V CMOS mixer with high linearity

Wang-Chi Cheng Wang-Chi Cheng,Cheong-Fat Chan Cheong-Fat Chan,Chiu-Sing Choy Chiu-Sing Choy,Kong-Pang Pun Kong-Pang Pun

doi:10.1109/apccas.2002.1114896

A 900 MHz 1.2 V CMOS mixer with high linearity

Wang-Chi Cheng Wang-Chi Cheng, Cheong-Fat Chan Cheong-Fat Chan + Show 2 more

https://doi.org/10.1109/apccas.2002.1114896

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Publication Date: Oct 28, 2002

Citations: 5

Affiliation: Chinese University of Hong Kong

#CMOS Down-conversion Mixer #CMOS Mixer + Show 8 more

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Abstract

A CMOS down-conversion mixer, using a current mode multiplication technique, is demonstrated in this paper. Apart from low voltage operation, the new mixer has a very good linearity; the measured IIP/sub 3/ (third-order input intercept point) is equal to 9.5 dBm. The new mixer circuit is specially designed for low voltage communication circuits using RF CMOS. The operating voltage is 1.2 V and the measured power consumption of the mixer is 3 mW.

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