A 9-bit 215 MS/s Folding-Flash Time-to-Digital Converter Based on Redundant Remainder Number System in 45-nm CMOS

Abstract

The first folding-flash time-to-digital converter (TDC) based on the remainder number system (RNS) is reported. In this paper, fine quantization of an input time interval is performed directly with dual free-running ring oscillators without additional circuitry to record the coarse bits. The RNS architecture reduces hardware complexity significantly without speed impairment relative to the full flash counterpart employing delay chains. As a proof-of-concept design, 490 quantization levels using only 84 delay stages achieve a sample rate of 215 MS/s and an LSB size of 9.4 ps. Without trimming or calibration, the measured differential nonlinearity and integral nonlinearity of the RNS TDC prototype are +0.53/−0.57 and +1.1/−1.1 LSBs, respectively.