Abstract
This paper presents a 9-bit 1 GS/s successive approximation register (SAR) analog-to-digital converter (ADC). In this hybrid architecture, the pseudo-pipeline operation is realized, which increases the sampling rate effectively. The ADC adopts two key technologies: the variable gain voltage-to-time converter (VTC), which ensures the linearity is not sacrificed; the segmented time-to-digital converter (STDC), which further improves the linearity of time domain quantization. The prototype ADC is simulated in a standard 65-nm CMOS process with an active area of 0.038 mm2. The simulated SNDR and SFDR are 44.3 and 58 dB with a sampling rate of 1 GS/s. The FoMW and FoMS are 24.7 fJ/conv-step and 150.7 dB, respectively.
Highlights
The higher data receiving rate in communication systems increases the demand for high-speed analog-todigital converter (ADC) in recent years
Time-domain quantization [7,8,9] is suitable for the high-speed successive approximation register (SAR) ADCs design, because the delay cell is faster due to the process scaling, but the operation in voltage-domain and time-domain is performed in sequence, with the improvement in speed limited
This paper presents a 9-bit 1-GS/s, single-channel, hybrid, voltage-time, pseudopipelined ADC in a 65-nm CMOS technology
Summary
The higher data receiving rate in communication systems increases the demand for high-speed ADCs in recent years. To increase the sampling rate of SAR ADCs, time interleaving technique [1,2,3,4] is used by multiplexing several converters in parallel. Compared with traditional SAR ADCs, time-domain quantization has better performance in terms of high-speed conversion, lowvoltage design, and reduction of mismatch. When the number of quantization bits is high, the capacitance in the Digital-to-Analog Converter (DAC) will increase exponentially, which limits the improvement of the conversion speed. Time-domain quantization [7,8,9] is suitable for the high-speed SAR ADCs design, because the delay cell is faster due to the process scaling, but the operation in voltage-domain and time-domain is performed in sequence, with the improvement in speed limited.
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