A 9.1-ENOB 6-mW 10-Bit 500-MS/s Pipelined-SAR ADC With Current-Mode Residue Processing in 28-nm CMOS

Abstract

This paper introduces a current-mode residue processing technique in a pipelined-successive-approximation register (SAR) analog-to-digital converter (ADC), which extends the operation speed of a single-channel ADC utilizing low-impedance-based signaling. A 10-bit pipelined-SAR ADC with featured building blocks such as a degenerated gm-cell as an open-loop residue amplifier, a switched-current mirror for sample-and-hold (S/H) function, and a split current digital-to-analog converter (DAC) for current-domain SAR conversion achieves a 500-MS/s conversion-rate under a 1.0-V supply. With background inter-stage mismatch calibration, a prototype ADC fabricated in a 28-nm CMOS process achieves 56.6-dB signal-to-noise-and-distortion ratio (SNDR) at a Nyquist input, resulting in a Walden figure of merit (FoM) of a 21.7-fJ/conversion-step.