Abstract
A static frequency divider is presented using 0.7 μm InP DHBTs with 280 GHz ft/fmax. The divider is based on ECL master–slave D-flip–flop topology with 30 HBTs and 20 resistors with a chip size 0.62 × 0.65 mm2. The circuits use peaking inductance as a part of the loads to maximize the highest clock rate. Momentum simulation is used to accurately characterize the effect of the clock feedback lines at the W band. Test results show that the divider can operate from 1 GHz up to 83 GHz. Its phase noise is 139 dBc/Hz with 100 kHz offset. The power dissipation of divider core is 350 mW.
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