Abstract
A new high-speed, low-power, and fast-lock all-digital delay-locked loop (DLL) for high-speed next-generation memory interface is presented. The proposed all-digital DLL utilizes a new 2-step time-to-digital converter (TDC) scheme which results in a fast-locking time of only 6 clock cycles, regardless of the long replica clock buffer (RCB) delay located in the feedback path of the DLL. The proposed DLL is designed in a 65 nm CMOS process, and it achieves a wide operating frequency range of 1.65–7.0 GHz without any harmonic lock problems. The proposed DLL dissipates 7.1 mW of power from a 1.0 V supply, achieves an effective peak-to-peak jitter of 4.55 ps at 7 GHz, and occupies an area of 0.02 mm2.
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