Abstract
This brief presents a 77-GHz 0.9-V wideband power amplifier (PA) with a digital power control scheme and two-way power combining. The power control is accomplished by digitally adjusting the width of the RF MOS to optimize the power added efficiency (PAE) of the PA. The proposed PA is implemented in a 28-nm CMOS process with a core chip area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.66 {\times }0$ </tex-math></inline-formula> .27 mm2. Measurement results show that the PA achieves a saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{P}_{SAT}$ </tex-math></inline-formula> ) of 12.15 dBm with a tuning range of 6.4-12 dBm at an input power of −5 dBm. The maximum PAE is 12% and the small signal gain is 23.6 dB at 81 GHz. The PA maintains a flat gain difference of ±2.12 to ±2.51 dB across a temperature range of −45-125°C when operating in the range of 76–81 GHz and has a 3-dB bandwidth of 16.1 GHz (72.9-89 GHz).
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