Abstract
The authors describe a 256-kb BiCMOS transistor-transistor logic (TTL)-compatible static RAM (SRAM) with typical address access time of 6 ns (5.0 V, 25 degrees C). The fast access time is due to the combination of new circuits and double-metal, double-polysilicon 0.8- mu m Hi-BiCMOS process technology. The high performance of the SRAM is due to the new BiCMOS circuit technologies. These include: (1) a low-input-capacitance BiCMOS gate, which reduced the gate loads in a decoder; (2) a reduced-load multiplexer-line sense amplifier; and (3) the two-level-presetting architecture of the TTL output buffer, which reduced the output-drive-current change rate to 20 mA/ns for a *8-b configured chip with a propagation delay time of 1.5 ns. The current change rate is about half that of the conventional-type output buffer. The fabricated SRAM is 4.25 mm*10 mm. >
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
