Abstract
This paper proposes an all-digital duty cycle corrector with synchronous fast locking, and adopts a new quantization method to effectively produce a phase of 180 degrees or half delay of the input clock. By taking two adjacent rising edges input to two delay lines, the total delay time of the delay line is twice the other delay line. This circuit uses a 0.18 μm CMOS process, and the overall chip area is 0.0613 mm2, while the input clock frequency is 500 MHz to 1000 MHz, and the acceptable input clock duty cycle range is 20% to 80%. Measurement results show that the output clock duty cycle is 50% ± 2.5% at a supply voltage of 1.8 V operating at 1000 MHz, the power consumed is 10.1 mW, with peak-to-peak jitter of 9.89 ps.
Highlights
In recent years, the development of CMOS process technology has driven the increased speed requirements for System-on-Chip (SoC), with clock signals widely used in most digital and mixed-signal circuits
In an Analog-to-Digital Converter (ADC) and Double-Data-Rate (DDR) SDRAM applications, both the positive and negative edges of the clock must capture data, the duty cycle must be close to 50%
The digital duty cycle correction circuit needs to generate a phase of 180 degrees
Summary
The development of CMOS process technology has driven the increased speed requirements for System-on-Chip (SoC), with clock signals widely used in most digital and mixed-signal circuits. The mismatch of the PMOS and NMOS transistors inside the inverter is a factor to alter duty cycle of input clock. This problem becomes more serious in circuits with higher speeds and clock buffers with more stages. This paper proposes a new architecture to generate a half-cycle of the input clock. This method mainly proposes using two adjacent rising edges of the input clock, respectively, input to two delay lines with different delay cell time. The proposed circuit architecture can achieve synchronization with the input signal and 50% duty cycle in 6 cycles.
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