A 68ns 4Mbit CMOS EPROM with high noise immunity design

Abstract

In a VLSI memory, noise generated by its own operation becomes a serious problem. The noise disturbs data sensing, especially in EPROM's which have a single-ended sensing scheme. To develop high- density and high-speed EPROM's, it is inevitably necessary to solve the noise problems. Incorrect EPROM functions due to the noise are dis- cussed in this paper. High-noise-immunity circuit techniques are proposed for stable data sensing and high-speed access time. Thesecare divided bit-line layout, reference line with dummy bit lines, and CE transition detector. Using these circuit techniques and 0.8- pm n-well CMOS technol- ogy, a 512K X 8-bit CMOS EPROM was developed. A 6&ns access time was achieved. The die sue is 5.62 mm X 15.30 mm and it is assembled in a 600-mil cerdip package.