Abstract
The aim of this paper is to present an LSI circuit specially designed for fault-tolerant systems. The circuit in question is a self-testing detection processor named PAD (a french acronym meaning self-testing detection processor). The purpose of the circuit is to enable the user to easily design and realize a fault-tolerant system with off-the-shelf ICs. The major part of this paper focuses on the design specifications of the chip which result from a preliminary study of different possible architectures for a fault-tolerant system.
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