Abstract
This paper presents a third order continuous time Delta Sigma modulator with a 4 bit internal quantizer sampling at 1GHz using an oversampling ratio of 10. Since dynamic element matching is ineffective at low oversampling and difficult to design within the loop at high sampling rates, a DAC linearization can be used in the digital domain to correct for non-linearities of DAC <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> . The presented modulator has been realized in a 1.2V, 90nm CMOS process and achieves an SNDR of 61.7 dB, DR of 67dB and an SFDR of 72dB within a 50MHz bandwidth. Overall, the modulator achieves a figure of merit of 207 fJ/conv.
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