A 6.7 MHz to 1.24 GHz $\text{0.0318}\;{\text{mm}^{\text{2}}}$ Fast-Locking All-Digital DLL Using Phase-Tracing Delay Unit in 90 nm CMOS

Abstract

In this paper, an all-digital delay-locked loop (ADDLL) with a phase-tracing delay unit (PTDU) has been proposed to achieve wide-operating frequency range, low power, and low cost. For the wide-range DLL, the long delay line is replaced by a PTDU which includes two gated ring oscillators (GROs) for generating the wide delay range with a reduced die area. According to the dual-loop control scheme in this work, the input clock rising edge and falling edge are tracked independently to ensure that the ADDLL output maintains the duty cycle of the input reference. Furthermore, the ADDLL utilizes an open-loop scheme to achieve fast lock time of five clock cycles for all supported input frequencies. The proposed ADDLL has been fabricated in TSMC 90 nm CMOS technology and supports a wide-operating frequency range from 6.7 MHz to 1.24 GHz within a small active area of ${0.0318}\;{\text {mm}^{2}}$ . The measured peak-to-peak and root-mean-square jitter at 1.24 GHz are 2.22 ps and 424.62 fs, respectively. The ADDLL consumes 14.5 mW while operating at 1.24 GHz.