A 65-nm High-Frequency Low-Noise CMOS-Based RF SoC Technology

Abstract

The radio-frequency (RF) performance of a 65-nm RF technology is assessed. The RF CMOS was fabricated with a physical gate length of 60 nm. In addition to the deep-n-well and p+-guard-ring isolation, a multi-poly-finger layout and fabrication process is optimized to improve the CMOS device RF performance. A superior cutoff frequency fT of 250 GHz and a maximum oscillation frequency f max of 220 GHz for the n-MOSFETs (NMOS) have been achieved. The minimum noise figures ( NF min's) are around 0.2 and 0.3 dB at 2.4 and 5.8 GHz, respectively. n+/n-well accumulation-mode MOS varactors, inductors, and metal-oxide-metal (MOM) capacitors are integrated with CMOS devices in a single chip by a standard logic process without extra masks. The tuning ratio of the varactor can be up to 12 with a peak quality (Q) factor of 20. The polysilicon-patterned ground shield and 3.7-?m-thick Cu metal process are implemented to improve the Q factor of the inductors. The structure and performance of the MOM and metal-insulator-metal capacitors are benchmarked, and a mesh structure is proposed to reduce the mismatch of the MOM capacitors.