Abstract
The integration of the power amplifier (PA) is one of the greatest challenges facing the designers of complex wireless SoCs. Recently, there has been a significant effort to implement PA's in CMOS [1–4]. The 802.11g standard utilizes OFDM modulation, which has a very high peak-to-average ratio (PAR) and therefore requires a highly linear PA. In addition, WLAN SoCs are evolving to accommodate more advanced applications, like the transmission and reception of multiple streams of high-definition video across long distances. This requires a higher linear transmit power. However, the low power supply, lossy substrate and lower breakdown voltage make the design of a linear, high power, high efficiency and reliable CMOS PA quite challenging. In this paper, a linear 65nm CMOS PA operating at 3.3V supply with an on-chip distributed LC power combining network and improved linearization is presented. The result is the highest combination of output power and efficiency yet reported for a packaged linear WLAN amplifier at 2.4GHz in a CMOS process.
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