Abstract
A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC . The particle momentum dicrimination capability represents the main challenge for this design together with the low power requirement: the constraint of low mass for the new tracker dictates a total power budget of less than 100 mW/cm2. The choice of a 65 nm CMOS technology has made it possible to satisfy this power requirement despite the fairly large amount of logic necessary to perform the momentum discrimination and the continuous operation at 40 MHz. Several techniques for low power have been used to implement this logic that performs cluster reduction, position offset correction and coordinate encoding. A prototype chip including a large part of the final functionality and the full front-end has been realized and comprises a matrix of 16 by 3 rectangular pixels of 100 μm × 1446 μm, providing 7.65 mm2 of segmented active area. Measurements of the analog front-end characteristics closely match the simulations and confirm the consumption of < 30 μA per pixel. Front-end characterization and irradiation results up to 150 MRad are also reported.
Highlights
A readout ASIC for the hybrid pixel detector with the capability of performing quick recognition of particles with high transverse momentum has been designed for the requirements of the CMS Outer Tracker at the High Luminosity LHC
The Macro Pixel ASIC (MPA) includes the front-end for the pixel detector, the memories where the whole event is stored for the Level-1 latency, and the Stub Finding logic
This paper describes the MPA-Light: the first MPA prototype designed in a 65 nm CMOS technology
Summary
The core of the PS module [5] consists mainly of the readout ASIC for the hybrid pixel detector, called Macro Pixel ASIC (MPA), and of a readout ASIC for strip detector, called Short Strip ASIC (SSA). The MPA includes the front-end for the pixel detector, the memories where the whole event is stored for the Level-1 latency, and the Stub Finding logic. The latter combines the strip data from the SSA and the pixel data from the MPA front-end to find the high pT particles for the L1 trigger decision. The details about the design of the full MPA can be found in [6]. This paper describes the MPA-Light: the first MPA prototype designed in a 65 nm CMOS technology
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