A 63 μg/√Hz Noise Floor and 14 pJ Power Efficiency Open-Loop MEMS Capacitive Accelerometer Using Closed-Loop Hybrid Dynamic Amplifier

Abstract

MEMS capacitive accelerometer for the Internet of Things (IoT) applications is designed with open-loop structure rather than close-loop structure to achieve low power consumption. In the open-loop structure, voltage control readout technique is preferred for low cost. However, voltage control readout technique suffers from poor noise performance and low power efficiency (in terms of FoM). In this paper, the weak feedback oversampling successive approximation readout circuit which merges the closed-loop hybrid dynamic amplifier with noise reduction technique is proposed to achieve low noise floor, high power efficiency and high accuracy. The proposed WFB-OSA based readout circuit is fabricated in a commercial <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18\mu \text{m}$ </tex-math></inline-formula> 1.8V CMOS process. The measurement result shows that the circuit has achieved a noise floor of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$63\mu g/\surd Hz$ </tex-math></inline-formula> and an FoM of 14pJ.