Abstract
In this paper, a fractional-N phase-locked loop (PLL) with an integrated chirp generation circuit block for frequency-modulated continuous-wave (FMCW) radar systems is reported. The circuit is composed of a push-push voltage controlled oscillator (VCO), a feedback divider including pre-scaler and programmable divider stages, a phase-frequency detector followed by a current steering charge pump, a sigma-delta modulator (SDM) with an 18-bit resolution, a chirp generator and a serial-peripheral-interface (SPI) for programming the chirp generator. The circuit occupies an area of 2.6 mm2, consumes 310 mW from a 3.3 V voltage supply. In integer-N mode, the PLL phase noise is better than -95 dBc/Hz at 1 MHz offset from 60 GHz center frequency. The rms frequency error is 134 kHz when the chirp slope is 0.4 GHz / 1.28 ms. The circuit is fabricated in a 0.13 μm SiGe BiCMOS technology. It is well suited for sub-harmonic transceiver frontend of an FMCW radar system at 122GHz and offers full programmability in ramp type, ramp duration and ramp bandwidth.
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