A 600 µA 32 kHz Input 960 MHz Output CP-PLL With 530 ps Integrated Jitter in 28 nm FD-SOI Process

Abstract

This paper presents a 32 kHz input and 960 MHz output low-power charge-pump phase-locked loop (CP-PLL) with a novel dual-path loop-filter for resistor noise reduction technique. The resistor noise reduction technique using dual-path loop-filter involves no “additional” active component; area/power overhead compared to the conventional CP-PLL. Reverse sub-threshold leakage compensated source-switched charge-pump (SS-CP) is employed in the PLL for improved reference spur performance. The PLL with minimum analog supply voltage of 1.62 V and minimum digital supply voltage of 0.65 V; with die area of 0.15 mm $^{2}$ is designed and fabricated in 28 nm STMicroelectronics FD-SOI process. The silicon measurement results have been included and the PLL performance includes total integrated jitter of 530 ps, reference spur of $-$ 65 dBc and current consumption of 600 $\mu$ A.