A 60-GHz Dual-Mode Distributed Active Transformer Power Amplifier in 65-nm CMOS

Abstract

This paper presents a 60-GHz power amplifier (PA) fabricated in a 65-nm CMOS technology. The proposed PA utilizes a dual-mode amplification circuit topology to achieve a high level of output power and efficiency in a small die area. High-output power is achieved by combining class AB cascode stage with a conventional class A common source (CS) stage in a compact four-way differential distributed active transformer to increase the amplifier’s power density. Driver stages consist of an enhanced cascode stage followed by a CS stage to achieve a high power (HP) gain. Fabricated in a 65-nm CMOS process, the maximum measured gain of the 60-GHz PA is 22 dB within a wide 3-dB bandwidth of 14 GHz. A maximum saturated output power of 19.7 dBm is measured in HP mode while consuming 430 mW over a 1.2 V core supply. In low-power (LP) mode of operation, the power gain of 20 dB and 19.7 dBm saturated power is measured at 60 GHz. The proposed dual-mode topology achieves an HP added efficiency of 25% and 19% in HP and LP modes, respectively.