Abstract
This paper presents a 60-GHz-band times12 multiplier and its application to a transceiver module. The multiplier consists of a quadrupler and a following tripler. For low dc power consumption, gatewidths of field-effect transistors are optimized. A cascode amplifier is adopted to obtain required output power levels. The fabricated multiplier exhibits output power higher than 0 dBm from 57 to 62 GHz with input power higher than -10 dBm. Spurious harmonic suppressions up to the 20th order are larger than 20 dBc with a desired 12th signal at a frequency of 60 GHz. DC power consumption is 185 mW. A transmitter module with the multiplier is assembled using a flip-chip bonding technique. Bit error rate is measured using amplitude shift-keying modulation with a data rate over 1 Gb/s
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callMore From: IEEE Transactions on Microwave Theory and Techniques
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
