A 60-GHz Band 2$\,\times\,$2 Phased-Array Transmitter in 65-nm CMOS

Abstract

A 60-GHz band 2 × 2 phased-array transmitter implemented in 65-nm bulk CMOS is described. Two-dimensional beam steering in the azimuthal and elevation planes is implemented via LO phase shifting in a transmitter that also supports direct or IF up-conversion. Full current bleeding in the final upconversion mixer suppresses flicker noise, and dynamic LO biasing suppresses carrier feedthrough. The 2.9 × 1.4 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip consumes a total of 590 mW from a 1-V supply when driving all four channels at a maximum saturated output power of 11 dBm, with 20 dB gain per transmitter. Carrier leakage varies between - 20.5 dBc ±0.5 dB and sideband rejection is 25 to 28 dBc among the four transmitters when measured on the same die. The measured phase noise is 1.7 ± 1 dB higher than the theoretical 21.6 dB increase in the phase noise due to 12 X frequency multiplication of the injected LO. Maximum power-added efficiency of the transmit amplifier is greater than 16%, and gain is above 17 dB from 54 to 61 GHz.