A 5kV ESD-protected 2.4GHz PA in 180nm RFCMOS optimized by ESD-PA co-design technique

Abstract

Electrostatic discharge (ESD) protection is required for all ICs. However, ESD protection inevitably introduce parasitic effects that will negatively affect IC performance, especially for parasitic-sensitive radio-frequency (RF) ICs. This paper reports design optimization of a 2.4GHz power amplifier (PA) circuit with 5kB full-chip ESD protection designed in an 180nm commercial RFCMOS technology. The PA design splits confirm that even an optimized ESD protection structure will affect PA circuit performance, which can be substantially recovered by careful PA-ESD co-design consideration.