A 5GHz low power receiver front-end RFIC with one tail current implemented in SiGe BiCMOS technology

Abstract

This paper presents a novel RF receiver front-end using only one shared tail current for low power application. The 5 GHz receiver front-end RFIC includes a voltage controlled oscillator (VCO), a double balanced mixer and a low noise amplifier (LNA) in a cascoded topology. The receiver RFIC was implemented in a 0.5 m SiGe BiCMOS technology. The VCO oscillation frequency is around 5 GHz, targeting at the WLAN 802.11a application. The VCO phase noise was measured around -105 dBc/Hz at 1 MHz frequency offset. Intermediate frequency (IF) output is centered at frequency of 600 MHz using a low-IF architecture and the conversion gain is measured more than 15 dB. The 1 dB gain compression point and sensitivity of the frontend is measured greater than -14 dBm and smaller than - 60 dBm respectively. The front-end core consumes 3.3 mA current from a 3.3 V power supply and occupies 1.4 mm2 area.