A 5-bit 300–900-MS/s 0.8–1.2-V Supply Voltage ADC With Background Self-Calibration

Abstract

Low-power, high-speed, and low-resolution analog-to-digital converters (ADCs) are mandatory for a wide range of modern applications. In this brief, a background-calibrated low-power 5-bit comparator-based binary-search ADC is presented. The ADC, which was implemented in a 130-nm complementary metal–oxide–semiconductor process, can compensate for process–voltage–temperature variations on-the-fly and offers state-of-the-art figure of merit (FoM) for the set of specifications. Multiple track-and-hold working in time interleaving are employed to enable increased conversion speed at low power consumption, whereas the comparator stages operate in amplifierless pipelining. As the comparators present a significant offset spread due to process variations, the thresholds are concurrently calibrated with the conversion using a reference digital-to-analog converter. The ADC operates with supply voltages ranging from 0.8 to 1.2 V. When supplied with 0.8 V, the ADC performs up to 300 MS/s and presents 28.13 dB, 235 $\mu\text{W}$ , and 39.4 fJ/conversion step of signal-to-noise-and-distortion ratio (SNDR), power consumption, and FoM, respectively. With 1.2 V of supply, the ADC performs up to 900 MS/s and presents 27.83 dB of SNDR, 1.54 mW of power consumption, and 82.5 fJ/conversion step of FoM.