A 5.6-GHz Class-DE Power Amplifier with Reduced Voltage Stress in 22-nm FDSOI CMOS

Abstract

This paper presents a 5.6 GHz Class-DE power amplifier (PA) with reduced voltage stress compared to classical PA designs. CMOS PAs are susceptible to a number of breakdown phenomena such as drain oxide breakdown and hot-carrier injection (HCI) which can significantly reduce their lifespan. The Class-DE amplifier is a hard-switching device which minimizes voltage-current overlap across the channel which significantly reduces the risk of HCI effects. The PA does not use an RF choke which limits the peak drain voltage to V DD , limiting the risk of drain oxide breakdown. The driver circuit gives a duty cycle below 50% and ensures that each transistor is almost completely off before the other has turned on. The PA achieves 47.9% power-added efficiency, 22.2 dBm output power, and 28.2 dB gain with a single 2.2 V supply voltage. Transient simulations of the PA's drain currents and voltages confirm the low current-voltage overlap which shows that the PA has much less risk of HCI effects than classical PA designs.