Abstract
This paper presents a new optimized high-speed divide-by-8/9 dual modulus prescaler. Simulation results show 54% reduction in power consumption, 40% of speed improvement and almost 48% area reduction as compared to the conventional architecture. Power consumption in the proposed prescaler is reduced by eliminating one True-Single-Phase Clocked (TSPC) D Flip-Flop (DFF) from the standard divide-by-2/3 prescaler, replacing it with Pulse Extension Logic (PEL) circuit. Redundant stages from asynchronous divide-by-2 units were also removed to save more power and reduce more delay. The simulation results show that the prescaler is capable of running at 5.5[Formula: see text]GHz of maximum frequency with 1.9[Formula: see text]mW power consumption. The divider is implemented in 0.18[Formula: see text][Formula: see text]m CMOS technology with 1.8[Formula: see text]V power supply.
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