A 5.12-Gbps serializer circuit for front-end fast readout electronics of silicon pixelated detectors

Abstract

Advanced synchrotron radiation sources are major facilities for analyzing the formation and evolution of material structure in multidisciplinary research, owing to their high luminosity, low emittance, wide energy bandwidth and other characteristics. In China, several advanced synchrotron radiation sources are under construction, including the HEPS (High Energy Photon Source) and SHINE (Shanghai high repetition rate X-ray Free Electron Laser and extreme light facility). These facilities are poised to become major multidisciplinary research platforms in China. To meet the requirements of pixel detectors in these facilities, dedicated pixel readout chips are being developed, including HEPS-BPIX and HYLITE. This paper presents a high-speed serializer circuit developed in a commercial 130-nm CMOS technology for the full-scale (128 × 128) pixel readout chip of HYLITE, which requires a data rate of 4 Gbps currently. The serializer consists of a 16-to-1 binary-tree multiplexer, a ring-oscillating-based phase-locked loop (RO-PLL) and a current-mode logic driving stage with a multi-stage pre-amplifier. Test results demonstrate its expected functionality within a wide operating range from 0.52 Gbps to 5.5 Gbps. At 5.12 Gbps, the measured jitter values are about 2 ps for random jitter, 20 ps for deterministic jitter, and 47 ps for total jitter with a 10−12 bit error rate. Additionally, the horizontal and vertical eye openings are 0.84 UI and 72%, respectively. These positive results indicate that the serializer meets the requirements of HYLITE.