Abstract
This paper describes the design and implementation of a 16/spl times/16 packet-switching chip that is used as the primary building block in a flexible, output-buffered, packet-switching architecture, called Starburst. This device contains 50,000 transistors implemented in a 1.2 /spl mu/m CMOS process. Even with a very conservative two-phase clocking methodology and static logic, it can be clocked at 50 MHz. Sixteen chips have been used to construct a prototype 16/spl times/16 Starburst ATM switch with a maximum throughput of 2.5 Gbits/sec.
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