A 500 MHz microprocessor with a very long instruction word architecture

Abstract

A 32-b very-long-instruction-word (VLIW) chip fabricated in a double-metal 1.5- mu m CMOS process using e-beam direct-write-on-wafer lithography is discussed. The chip contains 77 K transistors on 78 mm/sup 2/. It is dedicated to running scalar integer applications. The chip consists of several independent functional units controlled on a cycle-by-cycle basis by a 200-b instruction. All units are pipelined and all stages operate in lock step, controlled by a single global clock. All units are connected to a shared on-chip multiport memory from which they take operands and into which they write results. Any previously computed result can be used as any operand of any unit. Ideally, six native operations can be initiated every cycle. In practice, the utilization of units will depend on the fine-grain parallelism that the application provides. Each unit (except the constant unit) gets an extra Boolean operand from the multiport guard memory. The guard controls whether the operation scheduled on the unit completes and whether the operation has any side effect on the processor state, such as completing a store or raising an arithmetic exception. All guards are independent and are used efficiently by the compiler to reduce the branch delay penalty drastically. A special design is required to get the necessary bandwidth from the multiport memory. >