Abstract
HYPRES has developed a monolithic on-chip phase-locked loop (PLL) for the stabilizing and locking of the high-frequency output of an single flux quantum (SFQ) clock source, using rapid single flux quantum (RSFQ) logic family elements for phase detection and frequency detection. This PLL was successfully fabricated and operated as a 50 GHz clock phase-locked to a MHz frequency external source. We were able to employ a feedback loop filter to correct the voltage bias on the SFQ clock and compensate for the frequency fluctuations created by voltage noise in the bias and shunt resistors. This effort resulted is a stable SFQ clock which is tunable and phase-locked to an external signal of lower frequency, and which does not increase the heat load of a circuit. Moreover, in addition to high speed synchronized clock sources, this PLL can now be used to implement new and useful devices, such as phase demodulators and clock recovery circuits.
Sign-in/Register to access full text options 
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
