Abstract
This paper describes the energy-efficient realization of a QPSK optical receiver (CoRX) for short-reach intra-datacenter interconnects based on analog coherent detection. The CoRX comprises inphase and quadrature channels for each polarization and a high-speed phase-frequency detector (PFD) that provides feedback to stabilize an optical local oscillator (LO) and maintain coherence with the received optical signal. Each receive (RX) channel consists of a transimpedance amplifier (TIA) based on a Cherry-Hooper emitter follower (CHEF). The electronic RX is implemented in a 130-nm SiGe HBT technology ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{T} = 300$ </tex-math></inline-formula> GHz), consumes 534 mW of DC power for a total electrical RX energy efficiency of 5.34 pJ/bit, and occupies 2.8 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$mm^{2}$ </tex-math></inline-formula> . Electrical characterization of the CoRX on an FR-4 PCB assembly demonstrates operation up to 60 GBaud with a bit error rate (BER) of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">−12</sup> . A co-packaged optical/electrical CoRX assembly with a silicon photonic receiver is characterized using a commercial-off-the-shelf quadrature phase-shift keying (QPSK) transmitter for constellations up to 50 GBaud (100 Gbps) at BER below KP4-FEC ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.2\times 10^{-4}$ </tex-math></inline-formula> ).
Highlights
I NTRA-DATA center (IDC) interconnects are trending toward aggregate data rates between 200 to 400 Gbps per wavelength for mid-reach lengths (< 2 km)
The total power consumption of a short-range coherent link, discounting the transmitter electronics, includes the optical power required for a minimum optical receiver sensitivity, PSENS, and the DC power required to amplify the signal to a sampling threshold, VI, VQ ≥ VMIN
The photonic integrated circuit (PIC) in this work is realized in the GF 9WG Silicon Photonic (SiPh) process and consists of a polarization splitter/rotator (PSR), optical hybrid (OH), and Ge photodiodes (PDs)
Summary
I NTRA-DATA center (IDC) interconnects are trending toward aggregate data rates between 200 to 400 Gbps per wavelength for mid-reach lengths (< 2 km). Digital coherent schemes using 56 Gbaud dualpolarization (DP)-QPSK and 28 Gbaud DP-16QAM require analog-to-digital converters (ADCs) with high sampling rates (112 GS/s and 56 GS/s, respectively) and high effective number of bits. These ADCs currently consume nearly 2.8 W (0.7 W per ADC) for a 224 Gbps (112 Gbps per polarization) coherent RX, adding 12.5 pJ/bit of power consumption [2]. The reported results demonstrate the lowest energy efficiency and average input-referred noise current density for coherent detection
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