A 5 ns 1 Mb BiCMOS SRAM with ECL I/O interface

Abstract

A high-speed X-address decoding scheme with wired-OR bipolar predecoders and partial decoding level converters is presented. In addition, a sensing scheme with small signal voltage swing (particularly for read bus lines) is described. These two high-speed schemes and a double-level polysilicon layer, double-level metal layer, 0.8- mu m BiCMOS process technology were used to implement a 5-ns address access time, 1-W power dissipation, and 1-Mb emitter-coupled logic input/output (I/O) interface SRAM (static random-access memory). >