A 5 GHz Fractional-<inline-formula> <tex-math notation="LaTeX">$N$</tex-math> </inline-formula> ADC-Based Digital Phase-Locked Loops With −243.8 dB FOM

Abstract

An ADC-based digital phase-locked loop (DPLL) assisted by a digital-to-time converter (DTC) is proposed for fractional- $N$ frequency synthesis. A successive approximation register (SAR) ADC is adopted to mimic the operation of the time-to-digital converter (TDC) in the conventional DPLL to achieve an equivalent 1-ps time-domain resolution. The superiority of ADC-based TDC is revealed and compared to delay-based TDC. The nonlinearity error induced by both TDC and DTC is also analyzed and discussed. Fabricated in a 40 nm CMOS technology, the proposed DPLL achieves an in-band phase noise $-$ 104 dBc/Hz and an integrated phase noise 379 $\text{fs}_{\mathrm{rms}}$ in the fractional- $N$ mode. The DPLL operates at 5 GHz with 2.92-mW power dissipation from a 0.9-V power supply. The core parts only occupy 0.09-mm2 active area. The FoM of the DPLL can be as good as $-$ 243.8 dB.