A 5 Bit to 6 Bit Reconfigurable Delay Line ADC Implemented with Changing the Length of Delay Line for Digital DC-DC

Abstract

This paper implements a 5 bit to 6 bit reconfigurable delay line ADC implemented with changing the length of delay line for digital DC-DC. The comparator, 33 delay cells and the decoder of the ADC is shared to reduce the area and power when this ADC works and changes accuracy. A detect and control logic is designed to change the input offset current of every delay cell to protect the delay line work correctly when the accuracy of ADC is reconstructed. Circuit performance is analyzed theoretically and simulated under CSMC 0.5um process. This paper designs a window delay line ADC whose voltage sensing range is 1.352V to 1.448V, LSB is 3mV or 1.5mV and sampling frequency is 4Mhz.