Abstract
The scaling of CMOS technology together with continued innovations in circuit and system design techniques is fueling a rising demand for increasingly high throughput serial data interfaces. However, advances in CMOS technology have little impact on channel performance, making channel impairments a bottleneck in wireline links. Furthermore, links are typically designed to cover multiple standards and are expected to operate over a wide range of data rates, making their design challenging [1-5]. This work presents a 4-lane 1.25–28.05Gb/s transceiver in 14nm FinFet technology. We measure a bit error rate (BER) lower than 1e-15 with a channel loss of 40dB at 28.05Gb/s.
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