A 4-KB 500-MHz 4-T CMOS SRAM using low-V/sub THN/ bitline drivers and high-V/sub THP/ latches

Abstract

The design of a prototypical 500-MHz CMOS 4-T SRAM is presented. The storage of data is realized by a pair of cross-coupled PMOS transistors, while the wordline controls a pair of NMOS transistors. The wordline voltage compensation circuit and bitline boosting circuit, then, are neither needed to enhance the data retention of memory cells. Built-in self-refreshing paths makes the data retention possible without the appearance of any external refreshing mechanism. Most important of all, low threshold voltage transistors are used in driving bit lines while high threshold voltage transistors are used in latching data voltages. The advantages of dual threshold voltage transistors can be used to reduce the access time and maintain data retention at the same time. Besides, a cascaded noise-immune ATD (address transition detector) is also included to filter out the unwanted CS (chip select) glitches when the SRAM is asynchronously operated.