A 4K CMOS gate array with automatically generated test circuits

Abstract

A 2-/spl mu/m CMOS 4K-gate array using a newly devised scan bus method has been developed. This method is applied to the array by using a double-latch structure, parallel scanning, and normal-test common pin techniques. The gate array can be tested for 95-100% of all DC faults using computer-generated test circuits and test data, without placing restrictions on the logic design. Due to an access-to-output flip-flop structure and a gate-isolated three-input type basic cell, including embedded transistors, the area increase and operating speed degradation due to test circuits are considerably reduced. Furthermore, besides the flip-flop blocks, a built-in RAM macroblock is available. Degradation of operating speed is evaluated as 10%. The scan operation is done at a clock cycle of 120 ns, and the access time of the RAM macroblock is 34 ns. The gate array includes 4032 three-input gates on a 7.2/spl times/7.02-mm chip.