Abstract

In this paper, an ultra-low jitter clock generator that employs a novel automatic frequency calibration (AFC) technique is presented. To achieve low jitter, the clock generator uses an LC-VCO with 5-bit switched tuning scheme. The clock output is taken from the output of a multi-modulus divider, which increases the output frequency range with small variation in the loop bandwidth. The capacitor array of the the VCO is controlled by a novel AFC technique that performs binary search for fast calibration and fine search to select an optimum tuning curve. A prototype chip implemented in 0.13-µm CMOS process achieves 480 MHz to 1 GHz of output frequency while consuming 22 mW from a 1.2 V supply. The measured rms jitter and calibration time of the proposed clock generator are 940 fs at 600 MHz and 350 ns, respectively. These numbers are the fastest calibration time and one of the lowest jitter that have been reported in a clock generator.

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