A $4.7\mu \mathrm{A}$ Quiescent Current Synthesizable Digital Low Dropout Regulator in 28-nm CMOS

Abstract

Power consumption of digital block becomes critical issues more and more in system-on-a-chip. To reduce the power distribution, digital core's input voltage should be lower. However, as input voltage decreases steadily, performance or functionality of digital block are further influenced by PVT variation. In this matter, to regulate under- or near-threshold input voltage, digital low dropout regulators (D-LDO), which can operate at near-threshold voltage, are more utilized than conventional analog low dropout regulators (A-LDO). In this paper, synthesizable D-LDO is presented, whose barrel shifter operates at 10-80MHz for short settling time and low quiescent current. Also, its digital core can be synthesized all together except power transistor and load capacitor. The input voltage of the proposed D-LDO is 0.5V, and 0.45V is generated. It achieves 100ns settling time while load current increases by 1mA. The D-LDO's quiescent current is $4.7{\mu} \mathrm{A}$ .