A 45nm CMOS 13-port 64-word 41b fully associative content-addressable register file

Abstract

The high-performance needs of mobile products has motivated CPU designers to increase processing performance while decreasing power consumption. A dual-issue out-of-order superscalar ARMv7-architecture CPU uses the technique of register-renaming to resolve write-after-read and write-after-write data hazards associated with register file (RF) operands. Register-renaming increases processing throughput by increasing instruction parallelism through the avoidance of many hazard-induced pipeline stalls. The RF is a 64-word, 41-bit fully-associative content-addressable array with three CAM-write ports, four RAM-write ports, and six read ports. The RF incorporates many low-power circuit and micro-architectural techniques unseen in prior similar RFs [1,2], such as gated-xnor static comparators, tri-state floating read bitlines, and read wordline gating to prevent unnecessary RF reads.