Abstract

The operation of a 45-GHz, Silicon/Silicon Germanium transmitter chipset including a 2×2 power amplifier (PA) array and an I/Q modulator with digital predistortion (DPD) linearization is demonstrated. The 2×2 PA array is implemented in a 45-nm SOI CMOS process and feeds a 2×2 antenna array implemented on a printed circuit board (PCB). The I/Q modulator is implemented in a 120-nm SiGe BiCMOS process where the LO input and RF output are also wire-bonded to a PCB and is programmed through an FPGA to compensate I/Q imbalance and LO leakage. The Si/SiGe transmitter chipset achieves 2.67% EVM at 9.375-MS/s symbol rate with 256-QAM, and 3.68% EVM at 25-MS/s symbol rate with 64-QAM. It produces an average EIRP of 28.6 dBm and consumes 1.7 W from the PA and 322 mW from the I/Q modulator after DPD.

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