A 434/868 MHz CMOS low-IF receiver with I/Q imbalance calibration for SRDs application

Abstract

A receiver for SRDs implemented by the 0.35 μm CMOS process is presented. The receiver, together with the ADC, power amplifier (PA), frequency synthesizer and digital baseband has been integrated into a single chip solution. Low cost and low power requirements are met by optimizing the receiver architecture and circuit topology. A simple mixed-signal mode I/Q imbalance calibration circuit is proposed to enhance the IRR (image rejection ratio) so as to raise the BER. From a single 3 V power supply, the receiver consumes 5.9 mA. The measurement result shows that the receiver achieves reference sensitivity of s−60 dBm and a control gain of 60 dB. The S11 reaches −20 dB at 433 MHz and −10 dB at 868 MHz without off-chip impedance match network. The die area is only 2 mm2 including the bias circuit.