A 40–170 MHz PLL-Based PWM Driver Using 2-/3-/5-Level Class-D PA in 130 nm CMOS

Abstract

A high-speed driver that provides a pulsewidth modulated output while using a class-D Power Amplifier (PA) is described. A PLL-based architecture is employed, which eliminates the requirement for a precise ramp or triangular signal generator, and a high-speed comparator, which are typically used in pulsewidth modulation (PWM) generation. Multilevel signaling is proposed to enhance back-off as well as peak efficiency, which is critical for signals with high peak-to-average power ratios (PAPRs). A differential folded PWM scheme is introduced to achieve highly linear operation. 3-level operation is achieved without the requirement for additional supply source or sink paths, while 5-level operation is achieved with an additional supply source/sink path compared with the 2-level operation. The PWM driver has been implemented in a 130 nm CMOS process and can operate with a switching frequency of 40–170 MHz. For the 2-/3-/5-level PA operation, with a 500 kHz sinusoidal input and 60 MHz switching frequency, the measured THD is −61/−62/−53 dB and the corresponding efficiency is 71%/83%/86% with 175/200/220 mW output power level, respectively. Performance has also been verified for 2-/3-level PA with a high PAPR signal with 500 kHz bandwidth. While intended as a general-purpose amplifier, the approach is well-suited for applications such as power-line communications.