A 40-nm Ultra-Low Leakage Voltage-Stacked SRAM for Intelligent IoT Sensors

Abstract

A stacked voltage domain SRAM is proposed as an effective leakage reduction technique where bit-cell arrays are split into two voltage domains (top and bottom) connecting in series between VDD and GND to generate a subthreshold retention voltage directly from a nominal supply with no area penalty or efficiency loss compared to the conventional voltage regulator approach. The Zigzag 8T bit-cell structure is chosen with an optimal transistor sizing to balance among hold stability, leakage, and area density. SRAM peripherals remains at full supply domain resulting in super-cutoff read for improved sensing margin and word-line overdrive for better write margin. A novel array swapping mechanism with a comprehensive timing control ensure stable access to arbitrary arrays within one system clock cycle. The proposed SRAM achieves 1.03-pW/b leakage at 0.58 V in 40 nm.