A 40 MHz-BW 12-bit continuous-time ∆Σ modulator with digital calibration and 84.2 dB-SFDR in 90 nm CMOS

Abstract

A 4th-order 40 MHz-BW 12-bit continuous-time delta-sigma modulator with digital calibration is presented. A cost-efficient current-shaping technique for the SC DAC is proposed to relax the OTA slewing requirement. The DAC static and dynamic mismatches are eliminated by a look-up table based digital calibration. With a 1.2 V power supply and a 960 MHz clock, 73.6 dB peak SNR and 76.3 dB DR are measured for a 40 MHz bandwidth. After calibration, the modulator achieves an excellent SFDR of 84.2 dB and a 72.9 dB peak SNDR, with IM3 better than 85 dB. The modulator consumes 69.6 mW power, and occupies 0.28 mm2 area in 90 nm CMOS.