A 4-stage 60-GHz low-noise amplifier in 65-nm CMOS with body biasing to control gain, linearity, and input matching

Abstract

A 4-stage 60-GHz low-noise amplifier is designed and laid out in a 65 nm CMOS technology. Transmission lines are used to realize the power matching networks at the input, output, and between the stages. Based on foundry-provided models, extensive electromagnetic simulations with Momentum® (a 2.5D simulator by Agilent) are performed on transmission lines, capacitors and I/O pads to model the behavior of the circuit at mm-wave frequencies. Furthermore, body biasing is used as a technique to control gain variability, linearity performance, and input matching of the designed LNA. Post-layout simulation results show that the LNA achieves a maximum gain of 21.3 dB at 60 GHz while consuming 20 mW from a 1.2 V supply. By changing the body bias voltage of the transistors in the two intermediate stages, the overall gain varies from 14 to 21.3 dB providing more than 7 dB of gain range. Adjusting the body biasing of the transistors in the last stage, results in a maximum IIP3 of more than 2 dBm for the overall amplifier. Also, the input return loss of the LNA is controlled by changing the bulk voltage of the input transistor in the first stage.